1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device such as a MEMS (Micro Electrical Mechanical System) device or MIST (Micro System Technology) device and, more particularly, to a trench side wall treatment following deep trench etching that employs a dry etching technology for forming a three-dimensional structure in a semiconductor substrate.
2. Description of the Related Art
In recent years, attention has been focused on microetching that utilizes semiconductor fine etching technologies to fabricate very minute structures of sizes on the order of a few 100 μm. The application of such minute structures in various sensors and in optical switches and high frequency (RF) products and so forth in the optical communication field has been studied.
Generally, because such microetching-applied products are fabricated using Si processes, these products can be integrated on a chip with a signal processing system LSI. As a result, a system having a certain single function can be built on a chip. Elements with such a function are known as MEMS devices in the U.S.A and MIST devices in Europe.
In order to fabricate the MEMS structure or device, etching generally with a width of several tens of μm, and a depth of several hundred μm or more (aspect ratio is 10 or more) is necessary, although such etching also varies depending on the intended structure. The aspect ratio is a value obtained by dividing lateral width by vertical width.
Such dimensions are very small values from the perspective of mechatronics products. However, from the perspective of the ultra LSI fabrication processes in recent years, which require fine etching technology of no more than 0.1 μm, the above-mentioned dimensions are very large values, i.e., large patterns are to be designed. For example, the dimensions are approximately one-thousand times the gate etching dimensions.
Therefore, the fine etching technology (in particular, the dry etching technology) that has been used to fabricate the semiconductors in recent years are often not applicable as is as the MEMS structure etching technology. For example, when silicon etching with large dimensions and a high aspect ratio is to be performed by using a plasma etching device that is employed in the fabrication of ordinary ultra LSIs, the etching speed drops significantly as the etching proceeds, and etching completely stops when a certain depth is reached.
This is deeply related to the basic etching reaction mechanism of silicon: the etching reaction advances while the etching reaction is induced upon bombardment with the etched surface of accelerated ions that enter the trench perpendicularly.
The mechanism of the etching stop is considered to be attributable to the following:
(1) When the trench becomes deeper in accordance with the progress of the etching, the estimated angle of the opening as viewed from the trench bottom becomes narrower and the ion oblique incidence component is shielded by the shadowing effect.
(2) The orbit of perpendicular incident ions changes according to the charge-up at the mask and trench bottom.
(3) Because the reaction product generated inside the trench is not readily exhausted from the trench and is retained, the internal pressure of the trench rises and, as a result, the scatter and bombardment with subsequent incident ions increase. Therefore, the flux of perpendicular incident ions that play a very important role in the etching progress drops.
In the etching process that is used in the fabrication of an ultra LSI in particular, etching is generally performed by establishing the simultaneous existence, in the same plasma atmosphere, of halogen types that serve to cause etching to progress (accelerated ions such as Cl+ or F+, F radicals, Cl radicals, and so forth, for example) and precursors having a surface deposition characteristic (polymerization characteristic) for suppressing side etching (CxFy radicals, for example).
The CxFy radicals are deposited not only on the trench side walls but also on the etched surface of the trench bottom and act to obstruct the etching. Therefore, in order to cause the etching to progress effectively, the etching reaction must be made to progress while removing the obstruction layer through sputtering by means of the bombardment of accelerated ions to expose the clean etched surface (silicon surface).
However, in the bottom of a trench with a width of several tens of μm and a depth of several hundred μm as required by the MEMS structure, it is hard to obtain the bombardment of sufficient ions with the etched surface for the above reasons and, as a result, the etching obstruction layer at the trench bottom cannot be adequately removed and, ultimately, the etching stops when a certain depth is reached.
Also, the total etching time is extremely long so that the mask material retreats during the etching and there is no mask material before the desired trench shape is obtained.
This is because accelerated ions with quite a large amount of energy must enter in order for etching to progress while the etching obstruction layer is removed through sputtering. In other words, this is because it is difficult to increase the mask selectivity.
One conventional approach for solving the problems associated with the etching of the MEMS structure is a trench etching process disclosed in U.S. Pat. No. 5,501,893 and Japanese Patent Application Kokai (Laid Open) No. 2000-299310. In this trench etching process, an etching step is separated from a deposition step, and the etching and deposition steps are alternately repeated. The etching step involves an etching reaction between halogen radicals or halogen ions and the silicon. The deposition step is depositing a side-wall protection film for suppressing the etching of the side wall portion.
In the above described approach, the trench etching of silicon is carried out by alternately repeating, for example, a silicon etching step and a step of depositing a fluorocarbon polymer film. The silicon etching step employs F radicals and F+ ions generated by means of SF6 gas plasma by using an etching apparatus of the inductively-coupled plasma (ICP) system. The deposition step deposits the fluorocarbon polymer film for side-wall protection by means of a polymer reaction and CxFy-type surface absorption that is generated as a result of dissociation in C4F8 gas plasma.
In the etching step employing SF6 plasma after the deposition step, the main role of the incident energetic F+ ions is to remove the deposited film from the silicon surface at the trench bottom to expose the silicon surface. The main etching mechanism following exposure of the silicon surface of the trench bottom is basically capable of promoting the etching reaction slightly for the F radicals absorbed on the exposed silicon surface upon the bombardment of ions onto the absorbed layer, but advances as a result of the chemical reaction between the silicon and F radicals (isotropic etching reaction). Originally, the F radicals and silicon react automatically at room temperature even in the absence of ion bombardment.
As understood from the above, if the etching step that employs SF6 plasma and the deposition step that employs C4F8 plasma are alternately repeated, there is absolutely no influence of an etching obstruction caused by CxFy radicals that are diffused onto the surface from the plasma during the etching step. Thus, even when the pattern has a high aspect ratio, the balance between the trench bottom etching and film deposition does not readily collapse and, hence, the etching stop does not readily occur. In other words, a process of superior stability is provided.
In addition, because a thick protection film is formed on the surface of the etching mask by the C4F8 plasma polymerization, a very high mask selectivity of at least 100 can be achieved even if a resist mask is used. As a result, deep silicon trench etching of at least 500 μm can be achieved without being accompanied by serious mask recession.
A CxFy plasma polymer film formed during irradiation with C4F8 plasma is deposited thickly on the trench side walls after the deep trench etching of silicon by means of the above described conventional method. Usually, when this deposited film is placed as is, the deposited film is detached nonuniformly and adheres as a foreign substance to the periphery of the trench while undergoing the subsequent process.
In particular, when the deposited film adheres on a moving part of the MEMS structure, a serious problem (i.e., operational defect) is produced. Therefore, it is very important that the plasma polymer film on the trench side walls be completely removed immediately after etching.
Normally, C4F8 gas is used as a portion of the etching gas when etching a SiO2 film in an ultra LSI fabrication process, and the CxFy plasma polymer film deposited on the underlying silicon and SiO2 pattern side walls following etching can be easily removed by oxide plasma ashing that is used in a normal ultra LSI fabrication process.
However, when the trench side walls undergo the deep trench etching using the ICP plasma etching apparatus, the deposited fluorocarbon plasma polymer film cannot be completely removed in the plasma ashing. This fact was ascertained by way of experimentation by the inventor. The inventor though that the causes include the strong promotion of dissociation by high-density ICP plasma (on the order of plasma density=1012 [/cm3]) of the ICP plasma etching apparatus, and the fact that the gas used in the deposition step is only C4F8.
The inventor thought that the C4F8 gas is highly dissociated in the plasma so that a film containing a large number of C—C bonds with a strong associative strength are formed and, as a result, detachment of the film becomes difficult. In addition, the inventor thought that the SiF4, which is the reaction product, is re-dissociated within the plasma and, consequently, Si is released in the plasma atmosphere and re-introduced to the film. Thus, the inventor thought that the resulting film is a rigid film containing an inorganic component that is not easily detached by oxide plasma alone.